Struct X2Apic 

pub struct X2Apic {
    _private: (),
}

Fields

_private: ()

Implementations

impl X2Apic

pub fn new() -> Option<Self>

pub fn is_supported() -> bool

pub fn enable(&self) -> Result<(), &'static str>

Enable x2APIC mode on this CPU.

Performs the two-step enable sequence:

1. Ensure APIC global enable (EN=1) in IA32_APIC_BASE.
2. Set x2APIC enable (EXTD=1).

Writes the Spurious Interrupt Vector Register to finalize.

Returns Err if the CPU refuses to enter x2APIC mode (e.g. BIOS locked the APIC base, or the CPU doesn’t actually support x2APIC).

pub fn read_and_clear_esr(&self) -> u32

Read and clear the Error Status Register.

After a send_ipi() the ESR should be read to detect delivery errors (illegal vector, accept error, etc.). Writes-1-to-clear, so we write 0 then read to snapshot.

pub fn id(&self) -> u32

pub fn version(&self) -> u32

pub fn eoi(&self)

pub fn send_ipi(&self, target_id: u32, vector: u8)

Send an IPI to a specific x2APIC destination.

Uses Fixed delivery mode, physical destination, edge-triggered, no shorthand. This is the common-case IPI (reschedule, TLB shootdown, etc.).

pub fn send_init_ipi(&self, target_id: u32)

Send an INIT IPI to a specific x2APIC destination.

INIT IPIs use Delivery Mode = 101 (INIT). In x2APIC mode the Level bit is not meaningful for INIT delivery, but is set to 1 (assert) by convention to match xAPIC-compatible INIT sequences.

pub fn send_startup_ipi(&self, target_id: u32, start_page: u8)

Send a STARTUP IPI (SIPI) to a specific x2APIC destination.

start_page is the start-up vector (page frame number of the real-mode entry point, e.g. 0x08 for physical 0x0800). The CPU begins execution at start_page << 12 in real mode after receiving SIPI.

pub fn configure_timer( &self, initial_count: u32, vector: u8, periodic: bool, divide: TimerDivide, )

Configure the LVT timer.

Programs the divide configuration, LVT entry, and initial count in the correct order (SDM requires: DIV → LVT → INIT_COUNT).

pub fn mask_timer(&self)

Mask the LVT timer (set mask bit = 1 → timer interrupt suppressed).

pub fn unmask_timer(&self)

Unmask the LVT timer (clear mask bit = 0 → timer interrupt delivered).