Module x2apic 

x2APIC (Extended xAPIC) driver

Provides MSR-based access to x2APIC registers instead of MMIO. x2APIC extends the APIC ID to 32 bits and uses MSRs for all register access.

Key differences from xAPIC:

• All registers accessed via MSRs (no MMIO).
• ICR writes are atomic single MSR writes (no delivery status polling needed).
• APIC ID is 32 bits (not just 8).
• ESR is write-1-to-clear (write 0 to ack, read for errors).

Structs

X2Apic

Enums

TimerDivide

Timer divide configuration values (IA32_X2APIC_TIMER_DIV, MSR 0x83E).

Constants

APIC_BASE_EN 🔒

APIC_BASE_EXTD 🔒

DELIVERY_FIXED 🔒

DELIVERY_INIT 🔒

DELIVERY_SIPI 🔒

DELIVERY_STARTUP 🔒

DEST_PHYSICAL 🔒

DEST_SHORTHAND_NONE 🔒

IA32_APIC_BASE_MSR 🔒

IA32_X2APIC_APICID 🔒

IA32_X2APIC_EOI 🔒

IA32_X2APIC_ESR 🔒

IA32_X2APIC_ICR 🔒

IA32_X2APIC_LVT_TIMER 🔒

IA32_X2APIC_SIVR 🔒

IA32_X2APIC_TIMER_DIV 🔒

IA32_X2APIC_TIMER_INIT 🔒

IA32_X2APIC_VERSION 🔒

LEVEL_ASSERT 🔒

LEVEL_DEASSERT 🔒

TRIGGER_EDGE 🔒

TRIGGER_LEVEL 🔒