Struct XhciController 

pub struct XhciController {

    mmio_base: usize,
    cap_regs: *const CapRegisters,
    op_regs: *mut OpRegisters,
    rt_regs: *mut RuntimeRegisters,
    db_regs: *mut u32,
    caplength: u8,
    max_ports: usize,
    ports: Vec<XhciPort>,
    device_ctx: *mut u8,
    device_ctx_phys: u64,
    cmd_ring: *mut Trb,
    cmd_ring_phys: u64,
    cmd_ring_deq: usize,
    cmd_ring_cycle: bool,
    event_ring: *mut Trb,
    event_ring_phys: u64,
    event_ring_deq: AtomicUsize,
    event_ring_cycle: AtomicBool,
    slot_id: AtomicU8,
    ctrl_transfer_buf: *mut u8,
    ctrl_transfer_buf_phys: u64,
    device_slots: Vec<Option<DeviceSlot>>,
}

Fields

mmio_base: usize

cap_regs: *const CapRegisters

op_regs: *mut OpRegisters

rt_regs: *mut RuntimeRegisters

db_regs: *mut u32

caplength: u8

max_ports: usize

ports: Vec<XhciPort>

device_ctx: *mut u8

device_ctx_phys: u64

cmd_ring: *mut Trb

cmd_ring_phys: u64

cmd_ring_deq: usize

cmd_ring_cycle: bool

event_ring: *mut Trb

event_ring_phys: u64

event_ring_deq: AtomicUsize

event_ring_cycle: AtomicBool

slot_id: AtomicU8

ctrl_transfer_buf: *mut u8

ctrl_transfer_buf_phys: u64

device_slots: Vec<Option<DeviceSlot>>

Implementations

impl XhciController

pub unsafe fn new(pci_dev: PciDevice) -> Result<Self, &'static str>

fn init(&mut self) -> Result<(), &'static str>

unsafe fn init_rings(&mut self) -> Result<(), &'static str>

unsafe fn init_interrupter(&mut self) -> Result<(), &'static str>

unsafe fn init_ctrl_transfer_buf(&mut self) -> Result<(), &'static str>

unsafe fn read_portsc(&self, port: usize) -> u32

unsafe fn write_portsc(&self, port: usize, val: u32)

unsafe fn read_usbcmd(&self) -> u32

unsafe fn write_usbcmd(&self, value: u32)

unsafe fn read_usbsts(&self) -> u32

unsafe fn write_crcr(&self, value: u64)

unsafe fn write_dcbaap(&self, value: u64)

unsafe fn write_config(&self, value: u32)

fn max_device_slots(&self) -> u32

fn max_ports_from_hw(&self) -> u32

unsafe fn cmd_ring_enqueue(&mut self, trb: Trb)

unsafe fn wait_for_event(&mut self) -> Result<Trb, &'static str>

unsafe fn ring_doorbell(&self, slot_id: u8, endpoint: u8)

unsafe fn alloc_input_context( &mut self, slot_id: u8, ) -> Result<(), &'static str>

unsafe fn alloc_transfer_ring( &mut self, slot_id: u8, endpoint: u8, ) -> Result<(), &'static str>

unsafe fn write_endpoint_context( &self, slot_id: u8, endpoint: u8, tr_phys: u64, max_packet: u32, ep_type: u32, interval: u32, )

unsafe fn reset_port(&self, port: usize) -> bool

fn enable_slot(&mut self) -> Result<u8, &'static str>

fn set_address(&mut self, slot_id: u8, address: u8) -> Result<(), &'static str>

pub fn setup_endpoint( &mut self, slot_id: u8, endpoint: u8, max_packet: u32, ep_type: u32, interval: u32, _max_burst: u32, ) -> Result<(), &'static str>

fn enumerate_all_ports(&mut self)

pub fn alloc_interrupt_buffer( &mut self, slot_id: u8, endpoint: u8, len: usize, ) -> Result<(*mut u8, u64), &'static str>

pub fn submit_interrupt_transfer( &mut self, slot_id: u8, endpoint: u8, ) -> Result<(), &'static str>

pub fn port_count(&self) -> usize

pub fn is_port_connected(&self, port: usize) -> bool

pub fn get_device_descriptor( &mut self, slot_id: u8, buf: &mut [u8; 18], ) -> Result<usize, &'static str>

pub fn get_configuration_descriptor( &mut self, slot_id: u8, config_idx: u8, buf: &mut [u8], len: usize, ) -> Result<usize, &'static str>

pub fn set_configuration( &mut self, slot_id: u8, config_value: u8, ) -> Result<(), &'static str>

pub fn set_protocol( &mut self, slot_id: u8, interface: u8, protocol: u8, ) -> Result<(), &'static str>

pub fn get_port_speed(&self, port: usize) -> u8

unsafe fn ctrl_transfer( &mut self, slot_id: u8, setup_data: &[u8; 8], data_buf: Option<&mut [u8]>, data_len: usize, ) -> Result<usize, &'static str>

Trait Implementations

impl Send for XhciController

impl Sync for XhciController