Structsยง
- CapRegisters ๐
- Device
Slot ๐ - Endpoint
Context ๐ - Input
Context ๐ - Input
Control ๐Context - Interrupter
Registers ๐ - OpRegisters ๐
- Runtime
Registers ๐ - Slot
Context ๐ - Trb ๐
- Xhci
Controller - Xhci
Port ๐
Constantsยง
- EP_
TYPE_ ๐CONTROL - EP_
TYPE_ ๐INTR_ IN - MAX_
ENDPOINTS ๐ - PORTSC_
CCS ๐ - PORTSC_
PED ๐ - PORTSC_
PP ๐ - PORTSC_
PR ๐ - PORTSC_
SPEED_ ๐SHIFT - PORTSC_
W1C_ ๐MASK - TRB_
CYCLE ๐ - TRB_
DIR_ ๐IN - TRB_
DIR_ ๐OUT - TRB_IDT ๐
- TRB_IOC ๐
- TRB_TC ๐
- TRB_
TD_ ๐SIZE_ MASK - TRB_
TD_ ๐SIZE_ SHIFT - TRB_
TYPE_ ๐ADDRESS_ DEVICE - TRB_
TYPE_ ๐CONFIGURE_ ENDPOINT - TRB_
TYPE_ ๐DATA_ STAGE - TRB_
TYPE_ ๐ENABLE_ SLOT - TRB_
TYPE_ ๐LINK - TRB_
TYPE_ ๐NORMAL - TRB_
TYPE_ ๐SETUP_ STAGE - TRB_
TYPE_ ๐SHIFT - TRB_
TYPE_ ๐STATUS_ STAGE - TRB_
TYPE_ ๐TRANSFER_ EVENT - USBCMD_
HCRST ๐ - USBCMD_
INTE ๐ - USBCMD_
RUN_ ๐STOP - USBSTS_
CNR ๐ - USBSTS_
HCH ๐ - XHCI_
MMIO_ ๐SIZE - XHCI_
PORT_ ๐REG_ BASE - XHCI_
PORT_ ๐REG_ STRIDE - XHCI_
RING_ ๐TRBS
Staticsยง
- XHCI_
CONTROLLERS ๐ - XHCI_
INITIALIZED ๐ - XHCI_
IRQ_ LINE