Struct GpioPin 

pub struct GpioPin {
    pub base: usize,
    pub offset: u32,
    pub active_low: bool,
}

A single memory-mapped GPIO line of the FPGA GPIO controller that backs the NBUS bit-banging protocol.

Register layout

The controller is expected to expose two 32-bit registers relative to base:

• base + 0x00: data register, bit offset drives/reflects the line;
• base + 0x04: direction register, bit offset set = output, cleared = input.

All accesses are volatile read-modify-write so concurrent lines of the same controller are preserved.

An unconfigured pin (base == 0) reports Self::is_configured == false; transactions that need it are rejected instead of silently doing nothing.

Fields

base: usize

Physical base address of the GPIO controller register block.

offset: u32

Bit index of this line within the controller’s 32-bit registers.

active_low: bool

When true, logical high/low are inverted relative to the electrical level.

Implementations

impl GpioPin

pub const DATA_REG_OFFSET: usize = 0x00

Offset of the data (set/clear via read-modify-write) register.

pub const DIR_REG_OFFSET: usize = 0x04

Offset of the direction register (bit set = output).

pub fn is_configured(&self) -> bool

Returns true when this pin points at a real controller (base != 0).

fn read_data(&self) -> u32

Reads the data register.

fn write_data(&self, val: u32)

Writes the data register.

fn rmw_bit(&self, reg_offset: usize, set: bool)

Sets or clears bit offset of a register via volatile read-modify-write.

pub fn set_high(&self)

Drives the line to its logical-high level.

pub fn set_low(&self)

Drives the line to its logical-low level.

pub fn get_value(&self) -> bool

Samples the current logical level of the line.

pub fn set_direction_input(&self)

Configures the line as input (direction bit cleared).

pub fn set_direction_output(&self)

Configures the line as output (direction bit set).