List of all items

Structs

• BusChild
• arm_cci::ArmCci
• arm_cci::CciPort
• arm_integrator_lm::ArmIntegratorLm
• brcmstb_gisb::BrcmstbGisb
• brcmstb_gisb::GisbErrorInfo
• brcmstb_gisb::GisbOffsets
• bt1_apb::Bt1Apb
• bt1_axi::AxiErrorInfo
• bt1_axi::Bt1Axi
• da8xx_mstpri::Da8xxMstpri
• da8xx_mstpri::MasterPriDescr
• da8xx_mstpri::MasterPriority
• hisi_lpc::HisiLpc
• imx_aipstz::AipstzConfig
• imx_aipstz::ImxAipstz
• imx_weim::CsTiming
• imx_weim::ImxWeim
• imx_weim::WeimDevtype
• intel_ixp4xx_eb::CsTimingConfig
• intel_ixp4xx_eb::IntelIxp4xxEb
• mips_cdmm::CdmmDevice
• mips_cdmm::MipsCdmm
• mmio::MmioRegion
• moxtet::Moxtet
• moxtet::MoxtetModule
• mvebu_mbus::MbusWindowData
• mvebu_mbus::MvebuMbus
• omap_l3_noc::ErrorInfo
• omap_l3_noc::L3FlagmuxData
• omap_l3_noc::L3MasterData
• omap_l3_noc::L3TargetData
• omap_l3_noc::OmapL3Noc
• omap_l3_smx::Omap3L3ErrorInfo
• omap_l3_smx::OmapL3Smx
• omap_ocp2scp::OmapOcp2Scp
• probe::ProbeResult
• qcom_ebi2::Ebi2CsConfig
• qcom_ebi2::QcomEbi2
• qcom_ssc_block_bus::QcomSscBlockBus
• scheme::BusSchemeServer
• scheme::OpenHandle
• simple_pm_bus::SimplePmBus
• stm32_etzpc::Stm32Etzpc
• stm32_firewall::FirewallEntry
• stm32_rifsc::Stm32Rifsc
• sun50i_de2::Sun50iDe2
• sunxi_rsb::RsbAddrMap
• sunxi_rsb::SunxiRsb
• tegra_aconnect::TegraAconnect
• tegra_gmi::GmiConfig
• tegra_gmi::GmiTiming
• tegra_gmi::TegraGmi
• ti_pwmss::TiPwmss
• ti_sysc::SyscQuirks
• ti_sysc::SyscRegbits
• ti_sysc::TiSysc
• ts_nbus::GpioPin
• ts_nbus::TsNbus
• uniphier_system_bus::BankConfig
• uniphier_system_bus::UniphierSystemBus
• vexpress_config::VexpressConfig

Enums

• BusError
• PowerState
• arm_cci::CciPortType
• moxtet::MoxtetModuleId
• omap_l3_noc::ErrorType
• probe::ProbeMode
• scheme::HandleKind
• stm32_firewall::FirewallType

Traits

• BusDriver
• stm32_firewall::FirewallController

Functions

• mmio::memory_barrier
• probe::make_region
• probe::probe_boundary_offsets
• probe::probe_clear_bits
• probe::probe_lifecycle
• probe::probe_memory_barrier
• probe::probe_modify32
• probe::probe_multi_width_overlap
• probe::probe_read_field32
• probe::probe_read_write_16
• probe::probe_read_write_32
• probe::probe_read_write_64
• probe::probe_read_write_8
• probe::probe_reinit
• probe::probe_set_bits
• probe::probe_walking_ones_32
• probe::probe_walking_ones_64
• probe::probe_write_field32
• probe::run_mmio_self_test
• probe::run_mmio_self_test_with_mode
• probe::zero_buf
• registry::init_all
• registry::try_init
• sunxi_rsb::ccr_clk_div
• sunxi_rsb::ccr_sda_out_delay
• sunxi_rsb::dar_da
• sunxi_rsb::dar_rta
• tegra_gmi::adv_width
• tegra_gmi::ce_width
• tegra_gmi::cs_select
• tegra_gmi::hold_width
• tegra_gmi::muxed_width
• tegra_gmi::oe_width
• tegra_gmi::wait_width
• tegra_gmi::we_width
• vexpress_config::cfg_ctrl_dcc
• vexpress_config::cfg_ctrl_device
• vexpress_config::cfg_ctrl_func
• vexpress_config::cfg_ctrl_position
• vexpress_config::cfg_ctrl_site

Constants

• arm_cci::CCI_CTRL_STATUS
• arm_cci::CCI_ENABLE_DVM_REQ
• arm_cci::CCI_ENABLE_REQ
• arm_cci::CCI_ENABLE_SNOOP_REQ
• arm_cci::CCI_PORT_CTRL
• arm_cci::COMPATIBLE
• arm_cci::MAX_POLL
• arm_cci::MAX_PORTS
• arm_cci::PORT_VALID
• arm_cci::PORT_VALID_SHIFT
• arm_integrator_lm::COMPATIBLE
• arm_integrator_lm::INTEGRATOR_AP_EXP_BASE
• arm_integrator_lm::INTEGRATOR_AP_EXP_STRIDE
• arm_integrator_lm::INTEGRATOR_SC_DEC_OFFSET
• arm_integrator_lm::NUM_SLOTS
• brcmstb_gisb::ARB_BP_CAP_CLEAR
• brcmstb_gisb::ARB_BP_CAP_STATUS_VALID
• brcmstb_gisb::ARB_BP_CAP_STATUS_WRITE
• brcmstb_gisb::ARB_ERR_CAP_CLEAR
• brcmstb_gisb::ARB_ERR_CAP_STATUS_TEA
• brcmstb_gisb::ARB_ERR_CAP_STATUS_TIMEOUT
• brcmstb_gisb::ARB_ERR_CAP_STATUS_VALID
• brcmstb_gisb::ARB_ERR_CAP_STATUS_WRITE
• brcmstb_gisb::BCM7038_OFFSETS
• brcmstb_gisb::BCM7278_OFFSETS
• brcmstb_gisb::BCM7445_OFFSETS
• brcmstb_gisb::COMPATIBLE
• bt1_apb::APB_EHB_ADDR
• bt1_apb::APB_EHB_ISR
• bt1_apb::APB_EHB_ISR_MASK
• bt1_apb::APB_EHB_ISR_PENDING
• bt1_apb::APB_EHB_TIMEOUT
• bt1_apb::APB_EHB_TIMEOUT_MAX
• bt1_apb::APB_EHB_TIMEOUT_MIN
• bt1_apb::COMPATIBLE
• bt1_axi::BT1_AXI_WERRH
• bt1_axi::BT1_AXI_WERRH_ADDR_MASK
• bt1_axi::BT1_AXI_WERRH_ADDR_SHIFT
• bt1_axi::BT1_AXI_WERRH_TYPE
• bt1_axi::BT1_AXI_WERRL
• bt1_axi::COMPATIBLE
• da8xx_mstpri::COMPATIBLE
• da8xx_mstpri::DA8XX_MSTPRI0_OFFSET
• da8xx_mstpri::DA8XX_MSTPRI1_OFFSET
• da8xx_mstpri::DA8XX_MSTPRI2_OFFSET
• da8xx_mstpri::MSTPRI_ARM_D
• da8xx_mstpri::MSTPRI_ARM_I
• da8xx_mstpri::MSTPRI_EDMA30TC0
• da8xx_mstpri::MSTPRI_EDMA30TC1
• da8xx_mstpri::MSTPRI_EDMA31TC0
• da8xx_mstpri::MSTPRI_EMAC
• da8xx_mstpri::MSTPRI_LCDC
• da8xx_mstpri::MSTPRI_PRU0
• da8xx_mstpri::MSTPRI_PRU1
• da8xx_mstpri::MSTPRI_SATA
• da8xx_mstpri::MSTPRI_UHPI
• da8xx_mstpri::MSTPRI_UPP
• da8xx_mstpri::MSTPRI_USB0
• da8xx_mstpri::MSTPRI_USB1
• da8xx_mstpri::MSTPRI_VPIF_DMA0
• da8xx_mstpri::MSTPRI_VPIF_DMA1
• hisi_lpc::CMD_OP_READ
• hisi_lpc::CMD_OP_WRITE
• hisi_lpc::CMD_SAMEADDR
• hisi_lpc::COMPATIBLE
• hisi_lpc::LPC_MAX_DWIDTH
• hisi_lpc::LPC_MAX_WAITCNT
• hisi_lpc::LPC_PEROP_WAITCNT
• hisi_lpc::LPC_REG_ADDR
• hisi_lpc::LPC_REG_CMD
• hisi_lpc::LPC_REG_OP_LEN
• hisi_lpc::LPC_REG_OP_STATUS
• hisi_lpc::LPC_REG_RDATA
• hisi_lpc::LPC_REG_STARTUP_SIGNAL
• hisi_lpc::LPC_REG_WDATA
• hisi_lpc::OP_STATUS_FINISHED
• hisi_lpc::OP_STATUS_IDLE
• hisi_lpc::STARTUP_SIGNAL_START
• imx_aipstz::COMPATIBLE
• imx_aipstz::IMX8MP_DEFAULT_CFG
• imx_aipstz::IMX_AIPSTZ_MPR0
• imx_weim::COMPATIBLE
• imx_weim::IMX1_WEIM
• imx_weim::IMX27_WEIM
• imx_weim::IMX50_WEIM
• imx_weim::IMX51_WEIM
• imx_weim::MAX_CS_COUNT
• imx_weim::MAX_CS_REGS_COUNT
• intel_ixp4xx_eb::BOOT_BASE
• intel_ixp4xx_eb::COMPATIBLE
• intel_ixp4xx_eb::CS_STRIDE
• intel_ixp4xx_eb::IXP456_EXP_PAR_EN
• intel_ixp4xx_eb::IXP4XX_EXP_BYTE_EN
• intel_ixp4xx_eb::IXP4XX_EXP_BYTE_RD16
• intel_ixp4xx_eb::IXP4XX_EXP_CNFG0
• intel_ixp4xx_eb::IXP4XX_EXP_CNFG0_MEM_MAP
• intel_ixp4xx_eb::IXP4XX_EXP_CS_EN
• intel_ixp4xx_eb::IXP4XX_EXP_CYC_TYPE_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_CYC_TYPE_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_HRDY_POL
• intel_ixp4xx_eb::IXP4XX_EXP_MUX_EN
• intel_ixp4xx_eb::IXP4XX_EXP_SIZE_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_SIZE_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_SPLT_EN
• intel_ixp4xx_eb::IXP4XX_EXP_T1_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_T1_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_T2_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_T2_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_T3_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_T3_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_T4_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_T4_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_T5_MASK
• intel_ixp4xx_eb::IXP4XX_EXP_T5_SHIFT
• intel_ixp4xx_eb::IXP4XX_EXP_WR_EN
• intel_ixp4xx_eb::MAX_CS
• intel_ixp4xx_eb::NORMAL_BASE
• mips_cdmm::CDMM_ACSR_DEVREV_MASK
• mips_cdmm::CDMM_ACSR_DEVREV_SHIFT
• mips_cdmm::CDMM_ACSR_DEVSIZE_MASK
• mips_cdmm::CDMM_ACSR_DEVSIZE_SHIFT
• mips_cdmm::CDMM_ACSR_DEVTYPE_MASK
• mips_cdmm::CDMM_ACSR_DEVTYPE_SHIFT
• mips_cdmm::CDMM_ACSR_SR
• mips_cdmm::CDMM_ACSR_SW
• mips_cdmm::CDMM_ACSR_UR
• mips_cdmm::CDMM_ACSR_UW
• mips_cdmm::CDMM_DRB_SIZE
• mips_cdmm::COMPATIBLE
• mips_cdmm::MAX_DRBS
• moxtet::COMPATIBLE
• moxtet::MAX_MODULES
• mvebu_mbus::COMPATIBLE
• mvebu_mbus::DDR_BASE_CS_OFF
• mvebu_mbus::DDR_SIZE_CS_MASK
• mvebu_mbus::DDR_SIZE_CS_OFF
• mvebu_mbus::DDR_SIZE_CS_SHIFT
• mvebu_mbus::DDR_SIZE_ENABLED
• mvebu_mbus::DDR_SIZE_MASK
• mvebu_mbus::MAX_WINS
• mvebu_mbus::MBUS_BRIDGE_BASE_OFF
• mvebu_mbus::MBUS_BRIDGE_CTRL_OFF
• mvebu_mbus::UNIT_SYNC_BARRIER_ALL
• mvebu_mbus::UNIT_SYNC_BARRIER_OFF
• mvebu_mbus::WIN_BASE_OFF
• mvebu_mbus::WIN_CTRL_ATTR_MASK
• mvebu_mbus::WIN_CTRL_ATTR_SHIFT
• mvebu_mbus::WIN_CTRL_ENABLE
• mvebu_mbus::WIN_CTRL_OFF
• mvebu_mbus::WIN_CTRL_SIZE_MASK
• mvebu_mbus::WIN_CTRL_SIZE_SHIFT
• mvebu_mbus::WIN_CTRL_SYNCBARRIER
• mvebu_mbus::WIN_CTRL_TGT_MASK
• mvebu_mbus::WIN_CTRL_TGT_SHIFT
• mvebu_mbus::WIN_REMAP_HI_OFF
• mvebu_mbus::WIN_REMAP_LO_OFF
• omap_l3_noc::CLEAR_STDERR_LOG
• omap_l3_noc::COMPATIBLE
• omap_l3_noc::CUSTOM_ERROR
• omap_l3_noc::L3_FLAGMUX_MASK0
• omap_l3_noc::L3_FLAGMUX_REGERR0
• omap_l3_noc::L3_TARG_STDERRLOG_CINFO_INFO
• omap_l3_noc::L3_TARG_STDERRLOG_CINFO_MSTADDR
• omap_l3_noc::L3_TARG_STDERRLOG_CINFO_OPCODE
• omap_l3_noc::L3_TARG_STDERRLOG_HDR
• omap_l3_noc::L3_TARG_STDERRLOG_INFO
• omap_l3_noc::L3_TARG_STDERRLOG_MAIN
• omap_l3_noc::L3_TARG_STDERRLOG_MSTADDR
• omap_l3_noc::L3_TARG_STDERRLOG_SLVOFSLSB
• omap_l3_noc::MAX_L3_MODULES
• omap_l3_noc::STANDARD_ERROR
• omap_l3_smx::COMPATIBLE
• omap_l3_smx::L3_AGENT_CONTROL
• omap_l3_smx::L3_AGENT_STATUS
• omap_l3_smx::L3_AGENT_STATUS_CLEAR_IA
• omap_l3_smx::L3_AGENT_STATUS_CLEAR_TA
• omap_l3_smx::L3_APP_BASES
• omap_l3_smx::L3_DEBUG_BASES
• omap_l3_smx::L3_ERROR_CODES
• omap_l3_smx::L3_ERROR_LOG
• omap_l3_smx::L3_ERROR_LOG_ADDR
• omap_l3_smx::L3_ERROR_LOG_CMD_MASK
• omap_l3_smx::L3_ERROR_LOG_CODE_MASK
• omap_l3_smx::L3_ERROR_LOG_CODE_SHIFT
• omap_l3_smx::L3_ERROR_LOG_INITID_MASK
• omap_l3_smx::L3_ERROR_LOG_INITID_SHIFT
• omap_l3_smx::L3_ERROR_LOG_MULTI
• omap_l3_smx::L3_ERROR_LOG_SECONDARY
• omap_l3_smx::L3_SI_FLAG_STATUS_0
• omap_l3_smx::L3_SI_FLAG_STATUS_1
• omap_ocp2scp::COMPATIBLE
• omap_ocp2scp::OCP2SCP_TIMING
• omap_ocp2scp::SYNC2_MASK
• omap_ocp2scp::SYNC2_SAFE_VALUE
• probe::REGION_SIZE
• probe::REGION_WORDS
• qcom_ebi2::COMPATIBLE
• qcom_ebi2::CS0_ENABLE
• qcom_ebi2::CS1_ENABLE
• qcom_ebi2::CS2_ENABLE
• qcom_ebi2::CS3_ENABLE
• qcom_ebi2::CS4_ENABLE
• qcom_ebi2::CS5_ENABLE
• qcom_ebi2::CS_ENABLE_MASKS
• qcom_ebi2::CS_FAST_OFFSETS
• qcom_ebi2::CS_SLOW_OFFSETS
• qcom_ebi2::EBI2_XMEM_CFG
• qcom_ebi2::EBI2_XMEM_CS0_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS0_SLOW_CFG
• qcom_ebi2::EBI2_XMEM_CS1_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS1_SLOW_CFG
• qcom_ebi2::EBI2_XMEM_CS2_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS2_SLOW_CFG
• qcom_ebi2::EBI2_XMEM_CS3_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS3_SLOW_CFG
• qcom_ebi2::EBI2_XMEM_CS4_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS4_SLOW_CFG
• qcom_ebi2::EBI2_XMEM_CS5_FAST_CFG
• qcom_ebi2::EBI2_XMEM_CS5_SLOW_CFG
• qcom_ebi2::FAST_ADDR_HOLD_ENA
• qcom_ebi2::FAST_ADV_OE_RECOVERY_SHIFT
• qcom_ebi2::FAST_RD_HOLD_SHIFT
• qcom_ebi2::NUM_CS
• qcom_ebi2::SLOW_RD_DELTA_SHIFT
• qcom_ebi2::SLOW_RD_WAIT_SHIFT
• qcom_ebi2::SLOW_RECOVERY_SHIFT
• qcom_ebi2::SLOW_WR_DELTA_SHIFT
• qcom_ebi2::SLOW_WR_HOLD_SHIFT
• qcom_ebi2::SLOW_WR_WAIT_SHIFT
• qcom_ssc_block_bus::AXI_HALTACK_REG
• qcom_ssc_block_bus::AXI_HALTREQ_REG
• qcom_ssc_block_bus::AXI_IDLE_REG
• qcom_ssc_block_bus::COMPATIBLE
• qcom_ssc_block_bus::MAX_HALT_WAIT
• qcom_ssc_block_bus::SSCAON_CONFIG0_CLAMP_EN_OVRD
• qcom_ssc_block_bus::SSCAON_CONFIG0_CLAMP_EN_OVRD_VAL
• qcom_ssc_block_bus::SSCAON_CONFIG1_CFG
• scheme::DRV_ERROR_COUNT
• scheme::DRV_REG_PREFIX
• scheme::DRV_RESUME
• scheme::DRV_STATUS
• scheme::DRV_SUSPEND
• scheme::FILEFLAG_DIRECTORY
• scheme::OPCODE_CLOSE
• scheme::OPCODE_OPEN
• scheme::OPCODE_READ
• scheme::OPCODE_READDIR
• scheme::OPCODE_WRITE
• scheme::PCI_PREFIX
• scheme::REPLY_MSG_TYPE
• scheme::STATUS_OK
• simple_pm_bus::COMPATIBLE
• stm32_etzpc::COMPATIBLE
• stm32_etzpc::ETZPC_DECPROT
• stm32_etzpc::ETZPC_HWCFGR
• stm32_etzpc::ETZPC_PROT_A7NS
• stm32_etzpc::HWCFGR_NUM_AHB_SEC_MASK
• stm32_etzpc::HWCFGR_NUM_AHB_SEC_SHIFT
• stm32_etzpc::HWCFGR_NUM_PER_SEC_MASK
• stm32_etzpc::HWCFGR_NUM_PER_SEC_SHIFT
• stm32_etzpc::HWCFGR_NUM_TZMA_MASK
• stm32_rifsc::CIDCFGR_CFEN
• stm32_rifsc::CIDCFGR_SCID_MASK
• stm32_rifsc::CIDCFGR_SCID_SHIFT
• stm32_rifsc::CIDCFGR_SEMEN
• stm32_rifsc::CIDCFGR_SEMWL_MASK
• stm32_rifsc::CIDCFGR_STRIDE
• stm32_rifsc::COMPATIBLE
• stm32_rifsc::EXPECTED_CID
• stm32_rifsc::HWCFGR2_CONF1_MASK
• stm32_rifsc::HWCFGR2_CONF2_MASK
• stm32_rifsc::HWCFGR2_CONF2_SHIFT
• stm32_rifsc::HWCFGR2_CONF3_MASK
• stm32_rifsc::HWCFGR2_CONF3_SHIFT
• stm32_rifsc::RIFSC_RISC_HWCFGR2
• stm32_rifsc::RIFSC_RISC_PER0_CIDCFGR
• stm32_rifsc::RIFSC_RISC_PER0_SEMCR
• stm32_rifsc::RIFSC_RISC_PRIVCFGR0
• stm32_rifsc::RIFSC_RISC_SECCFGR0
• stm32_rifsc::SEMCR_MUTEX
• sun50i_de2::COMPATIBLE
• sunxi_rsb::COMPATIBLE
• sunxi_rsb::DEFAULT_ADDR_MAP
• sunxi_rsb::MAX_POLL
• sunxi_rsb::RSB_ADDR
• sunxi_rsb::RSB_CCR
• sunxi_rsb::RSB_CMD
• sunxi_rsb::RSB_CMD_RD16
• sunxi_rsb::RSB_CMD_RD32
• sunxi_rsb::RSB_CMD_RD8
• sunxi_rsb::RSB_CMD_STRA
• sunxi_rsb::RSB_CMD_WR16
• sunxi_rsb::RSB_CMD_WR32
• sunxi_rsb::RSB_CMD_WR8
• sunxi_rsb::RSB_CTRL
• sunxi_rsb::RSB_CTRL_ABORT_TRANS
• sunxi_rsb::RSB_CTRL_GLOBAL_INT_ENB
• sunxi_rsb::RSB_CTRL_SOFT_RST
• sunxi_rsb::RSB_CTRL_START_TRANS
• sunxi_rsb::RSB_DAR
• sunxi_rsb::RSB_DATA
• sunxi_rsb::RSB_DMCR
• sunxi_rsb::RSB_DMCR_DEVICE_START
• sunxi_rsb::RSB_DMCR_MODE_DATA
• sunxi_rsb::RSB_DMCR_MODE_REG
• sunxi_rsb::RSB_INTE
• sunxi_rsb::RSB_INTS
• sunxi_rsb::RSB_INTS_LOAD_BSY
• sunxi_rsb::RSB_INTS_TRANS_ERR
• sunxi_rsb::RSB_INTS_TRANS_ERR_ACK
• sunxi_rsb::RSB_INTS_TRANS_ERR_DATA_MASK
• sunxi_rsb::RSB_INTS_TRANS_OVER
• sunxi_rsb::RSB_LCR
• tegra_aconnect::COMPATIBLE
• tegra_gmi::ADV_ACTIVE_HIGH
• tegra_gmi::BUS_WIDTH_32BIT
• tegra_gmi::COMPATIBLE
• tegra_gmi::CONFIG_GO
• tegra_gmi::CS_ACTIVE_HIGH
• tegra_gmi::MAX_CHIP_SELECT
• tegra_gmi::MUX_MODE
• tegra_gmi::OE_ACTIVE_HIGH
• tegra_gmi::RDY_ACTIVE_HIGH
• tegra_gmi::RDY_BEFORE_DATA
• tegra_gmi::TEGRA_GMI_CONFIG
• tegra_gmi::TEGRA_GMI_TIMING0
• tegra_gmi::TEGRA_GMI_TIMING1
• ti_pwmss::COMPATIBLE
• ti_sysc::COMPATIBLE
• ti_sysc::MAX_MODULE_SOFTRESET_WAIT
• ti_sysc::REGBITS_OMAP2
• ti_sysc::REGBITS_OMAP4
• ti_sysc::SYSC_IDLE_FORCE
• ti_sysc::SYSC_IDLE_NO
• ti_sysc::SYSC_IDLE_SMART
• ts_nbus::COMPATIBLE
• ts_nbus::MAX_POLL_RDY
• ts_nbus::TS_NBUS_DIRECTION_IN
• ts_nbus::TS_NBUS_DIRECTION_OUT
• ts_nbus::TS_NBUS_WRITE_ADR
• ts_nbus::TS_NBUS_WRITE_VAL
• uniphier_system_bus::COMPATIBLE
• uniphier_system_bus::MIN_BANK_SIZE
• uniphier_system_bus::UNIPHIER_SBC_BASE
• uniphier_system_bus::UNIPHIER_SBC_BASE_BE
• uniphier_system_bus::UNIPHIER_SBC_BASE_DUMMY
• uniphier_system_bus::UNIPHIER_SBC_CTRL0
• uniphier_system_bus::UNIPHIER_SBC_NR_BANKS
• uniphier_system_bus::UNIPHIER_SBC_STRIDE
• vexpress_config::COMPATIBLE
• vexpress_config::MAX_POLL_TRIES
• vexpress_config::SITE_DB1
• vexpress_config::SITE_DB2
• vexpress_config::SITE_MASTER
• vexpress_config::SITE_MB
• vexpress_config::SYS_CFGCTRL
• vexpress_config::SYS_CFGCTRL_START
• vexpress_config::SYS_CFGCTRL_WRITE
• vexpress_config::SYS_CFGDATA
• vexpress_config::SYS_CFGSTAT
• vexpress_config::SYS_CFGSTAT_COMPLETE
• vexpress_config::SYS_CFGSTAT_ERR
• vexpress_config::SYS_HBI_MASK
• vexpress_config::SYS_MISC
• vexpress_config::SYS_MISC_MASTERSITE
• vexpress_config::SYS_PROCID0
• vexpress_config::SYS_PROCID1