Module ahci 

AHCI (Advanced Host Controller Interface) driver : AHCI spec 1.3.1

PCI: class=0x01 (Mass Storage), subclass=0x06 (SATA), prog_if=0x01 MMIO base: BAR5 (ABAR)

Per-port memory layout (packed into one 4 KB page): [0x000..0x3FF] Command List (1024 B, 32 × 32-byte headers) [0x400..0x4FF] FIS receive (256 B) [0x500..0x5FF] Command table (128 B header + 1 × 16-byte PRDT)

IRQ-driven completion (DRV-02 v2)

When a task context exists (current_task_id() is Some), commands are completed via interrupt + WaitQueue::wait_until() so the issuing task blocks without busy-spinning. During early boot (no task yet) the legacy polling path is used as a fallback.

Per-port statics (indexed by port_num 0..32) are used so the IRQ handler can signal completion without acquiring any slow lock:

• PORT_VIRT[n] : MMIO virtual address of port n registers
• PORT_SLOT0_DONE[n] : set by IRQ handler when slot-0 completes
• PORT_SLOT0_ERROR[n]: set by IRQ handler when a task-file error fires
• PORT_WQ[n] : WaitQueue; issuing task blocks here

Re-exports

pub use super::virtio_block::BlockDevice;

pub use super::virtio_block::BlockError;

pub use super::virtio_block::SECTOR_SIZE;

Structs

AhciController

AhciPort 🔒

PendingAsyncReadCompletion 🔒

Enums

AhciError

Constants

ATA_IDENTIFY 🔒

ATA_READ_DMA_EXT 🔒

ATA_WRITE_DMA_EXT 🔒

CLB_OFF 🔒

CMDH_CTBA 🔒

CMDH_CTBAU 🔒

CMDH_FLAGS 🔒

CMDH_PRDTL 🔒

CMD_CR 🔒

CMD_FR 🔒

CMD_FRE 🔒

CMD_ST 🔒

CTAB_CFIS 🔒

CTAB_OFF 🔒

CTAB_PRDT 🔒

EFAULT 🔒

FB_OFF 🔒

FIS_CMD 🔒

FIS_CNT_HI 🔒

FIS_CNT_LO 🔒

FIS_C_BIT 🔒

FIS_DEVICE 🔒

FIS_FLAGS 🔒

FIS_LBA0 🔒

FIS_LBA1 🔒

FIS_LBA2 🔒

FIS_LBA3 🔒

FIS_LBA4 🔒

FIS_LBA5 🔒

FIS_LBA_MODE 🔒

FIS_TYPE 🔒

FIS_TYPE_H2D 🔒

GHC_AE 🔒

GHC_HR 🔒

GHC_IE 🔒

HBA_GHC 🔒

HBA_IS 🔒

HBA_PI 🔒

PORT_CI 🔒

PORT_CLB 🔒

PORT_CLBU 🔒

PORT_CMD 🔒

PORT_FB 🔒

PORT_FBU 🔒

PORT_IE 🔒

PORT_IS 🔒

PORT_SERR 🔒

PORT_SIG 🔒

PORT_SSTS 🔒

PORT_TFD 🔒

PXIE_DHRE 🔒

PXIE_TFEE 🔒

PXIS_TFES 🔒

SIG_SATA 🔒

SSTS_DET_COMM 🔒

SSTS_DET_MASK 🔒

TFD_BSY 🔒

TFD_DRQ 🔒

Statics

AHCI 🔒

AHCI_ABAR_VIRT 🔒

AHCI ABAR virtual address : written once during init, read by IRQ handler.

AHCI_IRQ_LINE

PCI interrupt line used by this controller.

PENDING_ASYNC_READ_COMPLETIONS 🔒

PORT_ASYNC_ACTIVE 🔒

Whether an async operation is in-flight on this port’s slot 0.

PORT_ASYNC_BUF_VADDR 🔒

User virtual address where read data must be copied (0 = write op).

PORT_ASYNC_DMA_PTR 🔒

Raw pointer to a leaked Box<DmaBuffer> held until IRQ completion. 0 means no buffer. Freed inside handle_interrupt() via Box::from_raw().

PORT_ASYNC_IS_WRITE 🔒

Whether the in-flight async command is a write operation.

PORT_ASYNC_LEN 🔒

Number of bytes transferred.

PORT_ASYNC_RING_ID 🔒

Ring id to push the completion CQE into (0 = no async pending).

PORT_ASYNC_USER_DATA 🔒

User-data token echoed in the completion CQE.

PORT_SLOT0_DONE 🔒

Per-port slot-0 completion flags : set by IRQ handler, cleared by consumer.

PORT_SLOT0_ERROR 🔒

Per-port slot-0 error flags : set by IRQ handler on task-file error.

PORT_VIRT 🔒

Per-port MMIO virtual addresses : written once during init.

PORT_WQ 🔒

Per-port wait queues : tasks block here while waiting for IRQ completion.

Functions

discard_deferred_async_read_completions 🔒

flush_deferred_async_read_completions 🔒

get_device

Return a reference to the first usable AHCI controller, if any.

handle_interrupt

Called from the IDT AHCI IRQ handler.

init

Scan the PCI bus for an AHCI controller and initialise it.

port_enable_irq 🔒

Enable interrupts for a port (DHRE = DMA completion, TFEE = errors).

port_rebase 🔒

Rebase port: assign our CLB/FB buffers then start the port.

port_start 🔒

Performs the port start operation.

port_stop 🔒

Performs the port stop operation.

rd32 🔒 ^⚠

Performs the rd32 operation.

submit_async_cmd 🔒

Submit a command asynchronously ; returns immediately without blocking.

submit_async_storage_op 🔒

Public entry point called from async_io::dispatch.

submit_cmd 🔒

Performs the submit cmd operation.

wr32 🔒 ^⚠

Performs the wr32 operation.