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strat9_kernel/hardware/amdgpu/
regs.rs

1//! AMDGPU MMIO register offsets (GCN/RDNA display controller).
2
3/// GPU identification
4pub const CHIP_ID: u32 = 0x0000;
5
6/// CRTC (CRT Controller)
7pub const CRTC_CONTROL: u32 = 0x6000;
8pub const CRTC_FB_BASE_LO: u32 = 0x6008;
9pub const CRTC_FB_BASE_HI: u32 = 0x600C;
10pub const CRTC_FB_PITCH: u32 = 0x6010;
11pub const CRTC_FB_SIZE: u32 = 0x6014;
12pub const CRTC_DIMENSIONS: u32 = 0x6018;
13pub const CRTC_H_TOTAL: u32 = 0x6020;
14pub const CRTC_V_TOTAL: u32 = 0x6024;
15pub const CRTC_FORMAT: u32 = 0x6028;
16
17/// GRBM (Graphics Register Bus Manager)
18pub const GRBM_GPU_STATUS: u32 = 0x09C0;
19pub const GRBM_RB_BACKEND_DISABLE: u32 = 0x09E8;