strat9_bus_drivers/
tegra_aconnect.rs

1use crate::{BusChild, BusDriver, BusError, PowerState, mmio::MmioRegion};
2use alloc::{string::String, vec::Vec};
3
4const COMPATIBLE: &[&str] = &["nvidia,tegra210-aconnect"];
5
6pub struct TegraAconnect {
7    regs: MmioRegion,
8    power_state: PowerState,
9    children: Vec<BusChild>,
10    ape_clk_enabled: bool,
11    apb2ape_clk_enabled: bool,
12}
13
14impl TegraAconnect {
15    /// Creates a new instance.
16    pub fn new() -> Self {
17        Self {
18            regs: MmioRegion::new(),
19            power_state: PowerState::Off,
20            children: Vec::new(),
21            ape_clk_enabled: false,
22            apb2ape_clk_enabled: false,
23        }
24    }
25
26    /// Performs the add child operation.
27    pub fn add_child(&mut self, child: BusChild) {
28        self.children.push(child);
29    }
30
31    /// Enables clocks.
32    pub fn enable_clocks(&mut self) -> Result<(), BusError> {
33        self.ape_clk_enabled = true;
34        self.apb2ape_clk_enabled = true;
35        Ok(())
36    }
37
38    /// Disables clocks.
39    pub fn disable_clocks(&mut self) {
40        self.ape_clk_enabled = false;
41        self.apb2ape_clk_enabled = false;
42    }
43}
44
45impl BusDriver for TegraAconnect {
46    /// Performs the name operation.
47    fn name(&self) -> &str {
48        "tegra-aconnect"
49    }
50
51    /// Performs the compatible operation.
52    fn compatible(&self) -> &[&str] {
53        COMPATIBLE
54    }
55
56    /// Performs the init operation.
57    fn init(&mut self, base: usize) -> Result<(), BusError> {
58        self.regs.init(base, 0x1000);
59        self.enable_clocks()?;
60        self.power_state = PowerState::On;
61        Ok(())
62    }
63
64    /// Performs the shutdown operation.
65    fn shutdown(&mut self) -> Result<(), BusError> {
66        self.disable_clocks();
67        self.power_state = PowerState::Off;
68        Ok(())
69    }
70
71    /// Performs the suspend operation.
72    fn suspend(&mut self) -> Result<(), BusError> {
73        self.disable_clocks();
74        self.power_state = PowerState::Suspended;
75        Ok(())
76    }
77
78    /// Performs the resume operation.
79    fn resume(&mut self) -> Result<(), BusError> {
80        self.enable_clocks()?;
81        self.power_state = PowerState::On;
82        Ok(())
83    }
84
85    /// Reads reg.
86    fn read_reg(&self, offset: usize) -> Result<u32, BusError> {
87        if !self.regs.is_valid() {
88            return Err(BusError::InitFailed);
89        }
90        Ok(self.regs.read32(offset))
91    }
92
93    /// Writes reg.
94    fn write_reg(&mut self, offset: usize, value: u32) -> Result<(), BusError> {
95        if !self.regs.is_valid() {
96            return Err(BusError::InitFailed);
97        }
98        self.regs.write32(offset, value);
99        Ok(())
100    }
101
102    /// Performs the children operation.
103    fn children(&self) -> Vec<BusChild> {
104        self.children.clone()
105    }
106}
strat9_bus_drivers/tegra_aconnect.rs

strat9_bus_drivers/
tegra_aconnect.rs
