intel_ethernet/
lib.rs

1#![no_std]
2
3use nic_queues::{RxDescriptor, TxDescriptor};
4
5// ---------------------------------------------------------------------------
6// Legacy RX descriptor (Intel 8254x SDM §3.2.3)
7// ---------------------------------------------------------------------------
8
9#[repr(C)]
10#[derive(Clone, Copy, Default)]
11pub struct LegacyRxDesc {
12    pub addr: u64,
13    pub length: u16,
14    pub checksum: u16,
15    pub status: u8,
16    pub errors: u8,
17    pub special: u16,
18}
19
20const RX_DD: u8 = 1 << 0;
21
22impl RxDescriptor for LegacyRxDesc {
23    /// Sets buffer addr.
24    fn set_buffer_addr(&mut self, phys: u64) {
25        self.addr = phys;
26    }
27    /// Returns whether done.
28    fn is_done(&self) -> bool {
29        self.status & RX_DD != 0
30    }
31    /// Performs the packet length operation.
32    fn packet_length(&self) -> u16 {
33        self.length
34    }
35    /// Performs the clear status operation.
36    fn clear_status(&mut self) {
37        self.status = 0;
38        self.length = 0;
39        self.errors = 0;
40    }
41}
42
43// ---------------------------------------------------------------------------
44// Legacy TX descriptor (Intel 8254x SDM §3.3.3)
45// ---------------------------------------------------------------------------
46
47#[repr(C)]
48#[derive(Clone, Copy, Default)]
49pub struct LegacyTxDesc {
50    pub addr: u64,
51    pub length: u16,
52    pub cso: u8,
53    pub cmd: u8,
54    pub status: u8,
55    pub css: u8,
56    pub special: u16,
57}
58
59const TX_DD: u8 = 1 << 0;
60const TX_CMD_EOP: u8 = 1 << 0;
61const TX_CMD_IFCS: u8 = 1 << 1;
62const TX_CMD_RS: u8 = 1 << 3;
63
64impl TxDescriptor for LegacyTxDesc {
65    /// Sets buffer.
66    fn set_buffer(&mut self, phys: u64, len: u16) {
67        self.addr = phys;
68        self.length = len;
69    }
70    /// Sets eop ifcs rs.
71    fn set_eop_ifcs_rs(&mut self) {
72        self.cmd = TX_CMD_EOP | TX_CMD_IFCS | TX_CMD_RS;
73    }
74    /// Returns whether done.
75    fn is_done(&self) -> bool {
76        self.status & TX_DD != 0
77    }
78    /// Performs the clear operation.
79    fn clear(&mut self) {
80        *self = Self::default();
81    }
82}
83
84// ---------------------------------------------------------------------------
85// E1000 register offsets (shared by E1000 / E1000e / I210 families)
86// ---------------------------------------------------------------------------
87
88pub mod regs {
89    pub const CTRL: usize = 0x0000;
90    pub const STATUS: usize = 0x0008;
91    pub const EERD: usize = 0x0014;
92    pub const ICR: usize = 0x00C0;
93    pub const IMS: usize = 0x00D0;
94    pub const IMC: usize = 0x00D8;
95    pub const RCTL: usize = 0x0100;
96    pub const TCTL: usize = 0x0400;
97    pub const RDBAL: usize = 0x2800;
98    pub const RDBAH: usize = 0x2804;
99    pub const RDLEN: usize = 0x2808;
100    pub const RDH: usize = 0x2810;
101    pub const RDT: usize = 0x2818;
102    pub const TDBAL: usize = 0x3800;
103    pub const TDBAH: usize = 0x3804;
104    pub const TDLEN: usize = 0x3808;
105    pub const TDH: usize = 0x3810;
106    pub const TDT: usize = 0x3818;
107    pub const RAL0: usize = 0x5400;
108    pub const RAH0: usize = 0x5404;
109}
110
111pub mod ctrl {
112    pub const SLU: u32 = 1 << 6;
113    pub const RST: u32 = 1 << 26;
114}
115
116#[allow(dead_code)]
117pub mod rctl {
118    pub const EN: u32 = 1 << 1;
119    pub const SBP: u32 = 1 << 2;
120    pub const UPE: u32 = 1 << 3;
121    pub const MPE: u32 = 1 << 4;
122    pub const BAM: u32 = 1 << 15;
123    pub const BSIZE_2048: u32 = 0 << 16;
124    pub const SECRC: u32 = 1 << 26;
125}
126
127pub mod tctl {
128    pub const EN: u32 = 1 << 1;
129    pub const PSP: u32 = 1 << 3;
130    pub const CT_SHIFT: u32 = 4;
131    pub const COLD_SHIFT: u32 = 12;
132}
133
134#[allow(dead_code)]
135pub mod int_bits {
136    pub const TXDW: u32 = 1 << 0;
137    pub const LSC: u32 = 1 << 2;
138    pub const RXDMT0: u32 = 1 << 4;
139    pub const RXO: u32 = 1 << 6;
140    pub const RXT0: u32 = 1 << 7;
141}
142
143pub mod eerd {
144    pub const START: u32 = 1 << 0;
145    pub const DONE: u32 = 1 << 4;
146    pub const ADDR_SHIFT: u32 = 8;
147    pub const DATA_SHIFT: u32 = 16;
148}
intel_ethernet/lib.rs

intel_ethernet/
lib.rs
