intel_ethernet/
lib.rs

1#![no_std]
2
3use nic_queues::{RxDescriptor, TxDescriptor};
4
5// ---------------------------------------------------------------------------
6// Legacy RX descriptor (Intel 8254x SDM §3.2.3)
7// ---------------------------------------------------------------------------
8
9#[repr(C)]
10#[derive(Clone, Copy, Default)]
11pub struct LegacyRxDesc {
12    pub addr: u64,
13    pub length: u16,
14    pub checksum: u16,
15    pub status: u8,
16    pub errors: u8,
17    pub special: u16,
18}
19
20const RX_DD: u8 = 1 << 0;
21
22impl RxDescriptor for LegacyRxDesc {
23    fn set_buffer_addr(&mut self, phys: u64) {
24        self.addr = phys;
25    }
26    fn is_done(&self) -> bool {
27        self.status & RX_DD != 0
28    }
29    fn packet_length(&self) -> u16 {
30        self.length
31    }
32    fn clear_status(&mut self) {
33        self.status = 0;
34        self.length = 0;
35        self.errors = 0;
36    }
37}
38
39// ---------------------------------------------------------------------------
40// Legacy TX descriptor (Intel 8254x SDM §3.3.3)
41// ---------------------------------------------------------------------------
42
43#[repr(C)]
44#[derive(Clone, Copy, Default)]
45pub struct LegacyTxDesc {
46    pub addr: u64,
47    pub length: u16,
48    pub cso: u8,
49    pub cmd: u8,
50    pub status: u8,
51    pub css: u8,
52    pub special: u16,
53}
54
55const TX_DD: u8 = 1 << 0;
56const TX_CMD_EOP: u8 = 1 << 0;
57const TX_CMD_IFCS: u8 = 1 << 1;
58const TX_CMD_RS: u8 = 1 << 3;
59
60impl TxDescriptor for LegacyTxDesc {
61    fn set_buffer(&mut self, phys: u64, len: u16) {
62        self.addr = phys;
63        self.length = len;
64    }
65    fn set_eop_ifcs_rs(&mut self) {
66        self.cmd = TX_CMD_EOP | TX_CMD_IFCS | TX_CMD_RS;
67    }
68    fn is_done(&self) -> bool {
69        self.status & TX_DD != 0
70    }
71    fn clear(&mut self) {
72        *self = Self::default();
73    }
74}
75
76// ---------------------------------------------------------------------------
77// E1000 register offsets (shared by E1000 / E1000e / I210 families)
78// ---------------------------------------------------------------------------
79
80pub mod regs {
81    pub const CTRL: usize = 0x0000;
82    pub const STATUS: usize = 0x0008;
83    pub const EERD: usize = 0x0014;
84    pub const ICR: usize = 0x00C0;
85    /// Interrupt Throttling Rate (SDM §13.4.19).
86    /// Value in 256 ns units; 0 = no throttling,  approx. 1950 = 2000 irq/s (conservative).
87    pub const ITR: usize = 0x00C4;
88    pub const ICS: usize = 0x00C8;
89    pub const IMS: usize = 0x00D0;
90    pub const IMC: usize = 0x00D8;
91    pub const RCTL: usize = 0x0100;
92    pub const TCTL: usize = 0x0400;
93    pub const RDBAL: usize = 0x2800;
94    pub const RDBAH: usize = 0x2804;
95    pub const RDLEN: usize = 0x2808;
96    pub const RDH: usize = 0x2810;
97    pub const RDT: usize = 0x2818;
98    pub const RDTR: usize = 0x2820;
99    pub const RADV: usize = 0x282C;
100    pub const TDBAL: usize = 0x3800;
101    pub const TDBAH: usize = 0x3804;
102    pub const TDLEN: usize = 0x3808;
103    pub const TDH: usize = 0x3810;
104    pub const TDT: usize = 0x3818;
105    pub const TIDV: usize = 0x3820;
106    pub const TADV: usize = 0x382C;
107    pub const RAL0: usize = 0x5400;
108    pub const RAH0: usize = 0x5404;
109    pub const VET: usize = 0x0008;
110    pub const VFTA: usize = 0x5200;
111}
112
113pub mod ctrl {
114    pub const SLU: u32 = 1 << 6;
115    pub const RST: u32 = 1 << 26;
116}
117
118pub mod rctl {
119    pub const EN: u32 = 1 << 1;
120    pub const SBP: u32 = 1 << 2;
121    pub const UPE: u32 = 1 << 3;
122    pub const MPE: u32 = 1 << 4;
123    pub const BAM: u32 = 1 << 15;
124    pub const BSIZE_2048: u32 = 0;
125    pub const BSIZE_4096: u32 = 1 << 25;
126    pub const BSIZE_8192: u32 = 1 << 16 | 1 << 25;
127    pub const SECRC: u32 = 1 << 26;
128}
129
130pub mod tctl {
131    pub const EN: u32 = 1 << 1;
132    pub const PSP: u32 = 1 << 3;
133    pub const CT_SHIFT: u32 = 4;
134    pub const COLD_SHIFT: u32 = 12;
135}
136
137pub mod int_bits {
138    pub const TXDW: u32 = 1 << 0;
139    pub const TXQE: u32 = 1 << 1;
140    pub const LSC: u32 = 1 << 2;
141    pub const RXDMT0: u32 = 1 << 4;
142    pub const RXO: u32 = 1 << 6;
143    pub const RXT0: u32 = 1 << 7;
144    pub const MDAC: u32 = 1 << 9;
145    pub const RXCFG: u32 = 1 << 10;
146    pub const GPI0: u32 = 1 << 11;
147    pub const GPI1: u32 = 1 << 12;
148}
149
150pub mod eerd {
151    pub const START: u32 = 1 << 0;
152    pub const DONE: u32 = 1 << 4;
153    pub const ADDR_SHIFT: u32 = 8;
154    pub const DATA_SHIFT: u32 = 16;
155}
156
157/// RX descriptor status bits (SDM §3.2.3).
158pub mod rx_status {
159    pub const DD: u8 = 1 << 0;
160    pub const EOP: u8 = 1 << 1;
161    pub const IXSM: u8 = 1 << 3;
162    pub const UDP: u8 = 1 << 4;
163    pub const TCP: u8 = 1 << 5;
164    pub const IPCS: u8 = 1 << 6;
165    pub const PIF: u8 = 1 << 7;
166}
167
168/// RX descriptor error bits (SDM §3.2.3).
169pub mod rx_errors {
170    pub const CE: u8 = 1 << 0;
171    pub const SE: u8 = 1 << 1;
172    pub const SEQ: u8 = 1 << 3;
173    pub const CPRS: u8 = 1 << 4;
174    pub const TCPE: u8 = 1 << 5;
175    pub const IPE: u8 = 1 << 6;
176}
177
178/// TX descriptor status bits (SDM §3.3.3).
179pub mod tx_status {
180    pub const DD: u8 = 1 << 0;
181    pub const EC: u8 = 1 << 1;
182    pub const LC: u8 = 1 << 2;
183    pub const TU: u8 = 1 << 3;
184}
intel_ethernet/lib.rs

intel_ethernet/
lib.rs
